Navigator Probes

MIPS Navigator™ probes support all of the latest MIPS® cores and licensee processors in the MIPS32® family. You can get more details from this link: Navigator Probe technical information.

Installation and starting up the MIPS Navigator probes –see this doc Navigator Console Getting Started Guide

EJTAG connector interface, reset recommendations, and electrical characteristics (very important to insure correct probe operation in your target) Navigator Console Hardware Guide

More useful information about EJTAG can be found in the EJTAG Application Note

Video links and introduction to using the probe with the Navigator ICS Eclipse interface Navigator ICS Video page

Tips for using the probe console for hardware bring up and testing (coming soon)

PDtrace

PDtrace (Program and Data trace) is the implementation used for acquiring instruction execution plus load/store address and data cycles for MIPS cores (one exception is the M14K™ which has iFlowtrace).

A sample screen capture:

Execution trace with load/store cycles

PDtrace provides options for what information is included in the trace.  Choices can include:

• PC (program counter) tracing
• load cycles with addresses and/or data values
• store cycles with addresses and/or data cycles
• markers which include instruction cache misses, data cache misses, and/or function call-returns
• cycle accurate information indicated the number of clock cycles between instructions or data, primarily indicating stall counts
• additional stall cycle types for 74K and 1074K cores
• User trace messages from instrumenting of code that writes a 32-bit value into the trace

For 74K, 1004K, and 1074K cores, the PDtrace has a PC trace-off mode where only defined events will be traced.  These are

• Function call and return instructions plus exception entry and exit points
• HW instruction triggers
• HW data triggers which includes the data value of the load or store
• Performance counter overflow
• Choice of 1 to 4 performance counters to be stored immediately after the event

This event trace records execution points in the code and/or data accesses from global memory or memory-mapped peripheral registers along with detailed performance counter values at the time of the event, providing insight into what the code and core is doing at these measurement points.

iFlowtrace

iFlowtrace™ (Instruction Flow Trace) is a minimal resource instruction trace system for MIPS32® M14K™ and M4K® cores. See the iFlowtrace Specification

A sample screen capture of iFlowtrace shows execution of microMIPS instructions followed by MIPS32 instructions:

iFlowtrace showing microMIPS instructions followed by MIPS32 instructions

The M14K iFlowtrace has a special trace mode in which it can store just matches to HW instruction triggers or HW data triggers. It has the option of including a timestamp of the number of clock cycles between stores to record time information. Example:

iFlowtrace in special events trace mode, storing values written to a static variable and recording the number of cycles between writes

PC Sampling and Hot Spot Analyzer (HSA)

The Program Counter (PC) Sampling feature is available with MIPS32 M14K™, 24K®, 34K®, 74K, 1074K, and 1004K cores. It is built on the unique Zero Overhead Sampling feature in which the program counter is periodically sampled over EJTAG and these executed addresses are binned with the Hot Spot Analyzer Eclipse software running on the host PC. More information can be found at Hot Spot Analyzer.
An example of HSA output showing sample counts at the line number and instruction level is:

HSA mixed Source and Instruction sampling results